FIG. 1 is a schematic cross-sectional view illustrating a conventional nonvolatile memory device with a vertically stacked structure. For example, this nonvolatile memory device is disclosed in U.S. Pat. No. 8,278,170.
A common source line CSL is formed on a semiconductor substrate 100. The common source line CSL is an N-type doping region of the semiconductor substrate 100. Lower interlayer dielectric layers 111˜114 and lower conduction patterns LSL, WL0 and WL1 are alternately stacked on the semiconductor substrate 100.
Moreover, lower active pillars 136 run through the lower interlayer dielectric layers 111˜114 and the lower conduction patterns LSL, WL0 and WL1. In addition, the lower active pillars 136 are contacted with the semiconductor substrate 100. The inside of the lower active pillar 136 may be filled with a lower filling insulating layer 138.
Moreover, upper interlayer dielectric layers 151˜154 and upper conduction patterns DWL, WL2, WL3 and USL are alternately stacked on the uppermost lower interlayer dielectric 114.
Moreover, upper active pillars 164 run through the upper interlayer dielectric layers 151˜154 and the upper conduction patterns DWL, WL2, WL3 and USL and contact the lower active pillars 136. In addition, the upper active pillars 164 are contacted with the lower active pillars 136. The inside of the upper active pillars 164 may be filled with an upper filling insulating layer 166.
An information storage layer 171 is arranged between the active pillars 136 and 164 and the conductions patterns LSL, WL0˜WL3 and USL. The information storage layer 171 may be extended between the conduction patterns LSL, WL0˜WL3 and USL and the interlayer dielectric layers 111˜114 and 151˜154.
An electrode separation pattern 175 is disposed over the common source line CSL. In addition, the electrode separation pattern 175 run through the interlayer dielectric layers 111˜114 and 151˜154 and the conduction patterns LSL, WL0˜WL3 and USL. The bottom of the electrode separation pattern 175 is contacted with the semiconductor substrate 100.
An upper active pattern 177 is disposed on the upper filling insulating layer 166 and contacted with an inner side of the upper active pillars 164. The upper active pattern 177 and the upper part of the upper active pillars 164 may be doped with impurities in order to be collaboratively defined as a drain region 179.
Moreover, a bit line BL1 is disposed over the upper interlayer dielectric layer 154, the electrode separation pattern 175 and the drain region 179. Generally, plural cell strings (CSTR) are formed between the bit line BL1 and the semiconductor substrate 100. In FIG. 1, only two cell strings (CSTR) are shown.
FIG. 2 is a schematic equivalent circuit illustrating a conventional nonvolatile memory device with vertically stacked cell strings structure. The nonvolatile memory device comprises bit lines BL0˜BL2, word lines WL0˜WL3, a dummy word line DWL, an upper selection line USL, a lower selection line LSL, and plural common source lines CSL.
Moreover, plural cell strings CSTR are connected between the bit lines BL0˜BL2 and the common source lines CSL. Each of the cell string CSTR comprises a lower selection transistor LST, an upper selection transistor UST, plural memory cell transistors MCT and at least one dummy memory cell transistor DCT, which are connected with each other in series.
FIG. 3 is a table illustrating the operating voltages of the conventional nonvolatile memory device with a vertically stacked structure in different operating modes. In different operating modes, a control circuit (not shown) of the nonvolatile memory device may provide various voltages to corresponding lines.
For example, in an erase mode, an erase voltage Ver (21V) is provided to the semiconductor substrate 100, a ground voltage Vss is provided to all word lines WL0˜WL3, the upper selection line USL, the lower selection line LSL, the common source lines CSL and all bit lines BL0˜BL2 are floating, and an intermediate voltage VDWL is provided to the dummy word line DWL. The intermediate voltage VDWL is in the range between the ground voltage Vss and the erase voltage Ver.
In case that the memory cell transistor MCT corresponding to the word line one (WL1) and the bit line one (BL1) is intended to be programed in the program mode, the word line WL1 is the selected word line, and the other word lines (i.e. the word line zero (WL0), the word line two (WL2) and the word line three (WL3)) are non-selected word lines, the bit line one (BL1) is the selected bit line, and the other bit lines (i.e. the bit line zero (BL0) and the bit line two (BL2)) are non-selected bit lines.
In the program mode, a program voltage Vpam (15˜20V) is provided to the selected word line, a pass voltage Vpass (10V) is provided to the non-selected word lines, a power supply voltage Vcc is provided to the upper selection line USL and the non-selected bit lines, the ground voltage Vss is provided to the lower selection line LSL, the common source lines CSL, the selected bit line and the semiconductor substrate 100, and the intermediate voltage VDWL is provided to the dummy word line DWL. The intermediate voltage VDWL is in the range between the ground voltage Vss and the erase voltage Ver.
In case that the memory cell transistor MCT corresponding to the word line two (WL2) and the bit line two (BL2) is intended to be read in the read mode, the word line two (WL2) is the selected word line, and the other word lines (i.e. the word line zero (WL0), the word line one (WL1) and the word line three (WL3)) are non-selected word lines, the bit line two (BL2) is the selected bit line, and the other bit lines (i.e. the bit line zero (BL0) and the bit line one (BL1)) are non-selected bit lines.
In the read mode, a selected read voltage (0V) is provided to the selected word line, a non-selected read voltage (4.5V) is provided to the non-selected word lines, a turn-on voltage (4.5V) is provided to both the upper selection line USL and the lower selection line LSL, the ground voltage is provided to the common source lines CSL and the semiconductor substrate 100, the power supply voltage Vcc is provided to the selected bit line, a low voltage (0.8V) is provided to the non-selected bit lines, and the intermediate voltage VDWL is provided to the dummy word line DWL. The intermediate voltage VDWL is in the range between the ground voltage Vss and the erase voltage Ver.
The voltages listed in the table of FIG. 3 are ideal operating voltages of the conventional nonvolatile memory device with a vertically stacked structure. However, since the common source line CSL is the N-type doping region of the semiconductor substrate, the electrical resistance of the common source line CSL is higher than the electrical resistance of the conductor of bit lines (e.g. BL0) or word lines (e.g. WL0). The voltage drifting caused by the electrical resistance of the common source line CSL may induce erroneous actions of the conventional nonvolatile memory device with the vertically stacked structure in various operating modes.